Synopsys announced an expanded agreement with Samsung Foundry to develop a broad portfolio of IP to reduce design risk and accelerate silicon success for automotive, mobile, high-performance computing (HPC) and multi-die designs.
This agreement expands Synopsys' collaboration with Samsung to enhance the Synopsys IP offering for Samsung's advanced 8LPU, SF5, SF4 and SF3 processes and includes Foundation IP, USB, PCI Express, 112G Ethernet, UCIe, LPDDR, DDR, MIPI and more. In addition, Synopsys will optimize IP for Samsung's SF5A and SF4A automotive process nodes to meet stringent Grade 1 or Grade 2 temperature and AEC-Q100 reliability requirements, enabling automotive chip designers to reduce their design effort and accelerate AEC-Q100 qualification. The auto-grade IP for ADAS SoCs will include design failure mode and effect analysis (DFMEA) reports that can save months of development effort for automotive SoC applications.
John Koeter, senior vice president of product management and strategy for IP at Synopsys
Our extensive co-optimization efforts with Samsung across both EDA and IP help automotive, mobile, HPC, and multi-die system architects cope with the inherent challenges of designing chips for advanced process technologies. This extension of our decades-long collaboration provides designers with a low-risk path to achieving their design requirements and quickly launching differentiated products to the market.
Jongshin Shin, corporate executive vice president of Foundry IP Development at Samsung Electronics
Samsung's longstanding collaboration with Synopsys, as our primary IP partner, has benefited our mutual customers by providing access to high-quality IP through each generation of Samsung's technology advancements. Extending this partnership across Samsung's full range of advanced nodes gives designers access to the industry's broadest IP portfolio, enabling them to meet the performance, power and area requirements of their target applications with less risk and faster time-to-market.
