Sprint announced the availability of an open source NFV/SDN-based mobile core reference solution designed to significantly improve performance of the network core by providing a clean, streamlined, high-performance data plane for the packet core.
Known as C3PO (Clean CUPS Core for Packet Optimization – CUPS: Control & User Plane Separation), the solution uses standard high-volume server hardware and streamlines mobile core architecture by collapsing multiple components into as few network nodes as possible.
The availability of the solution is the result of four years of collaboration between Intel Labs and Sprint on a joint research effort to develop optimal DPDK-based data plane nodes and disaggregated evolved packet core architectures, as well as a platform for further 5G core infrastructure research.
In lab tests conducted on Dell EMC DSS 9000 rack scale infrastructure with compute sleds running dual socket 14 core Intel® Xeon processors E5-2680 v4, Sprint achieved 1.63 Mpps (million packets per second) throughput. This C3PO configuration demonstrated high efficiency by utilizing as few as seven processor cores - with one packet processing core and six processor cores supporting other tasks such as Control Plane, statistics, load balancer, operating system and other operations, for 500,000 subscribers using a typical Sprint traffic model. A similar C3PO configuration achieved 2.2 Mpps with a similar traffic model for 50,000 subscribers.
C3PO addresses bottlenecks in mobile core packet performance by separating and independently scaling the data plane and control plane. The C3PO architecture collapses multiple evolved packet core and SGi LAN elements in a single data plane instance. A serving gateway, packet gateway, deep packet inspection, child protection, carrier grade NAT, static firewall, and service function chaining, or any combination of these functions, can be collapsed into one data plane instance.