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How FPGAs Enable Wearable Technology

How FPGAs Enable Wearable Technology Image Credit: dolgachov/www.bigstockphoto.com

When it comes to wearable technology, there’s more to the market than Fitbits and Google Glass. There is a growing list of industrial use cases for wearables, be it in healthcare, logistics, or manufacturing. While several of these applications are gaining traction and making industrial processes easier, safer, and more efficient, others are hamstrung by network limitations, requiring either high bandwidth, low latency and jitter, or both.

As of 2019, the state of wearable technology in the industrial and enterprise world was primed for growth, with a market value of over $1.5 billion and projected increase of more than $3 billion over the following five years. This includes medical wearables, such as fitness trackers and biosensors; manufacturing wearables, containing hands-free collaboration tools, worker safety sensors, and smart thermal clothing; and wearables for logistics personnel, including digital eyewear (for package sorting status), data gloves, and wearable RFID/scanners.

These are only a few examples of how wearables are positioned to improve safety, efficiency, and convenience for industrial and enterprise workers.

There are also many promising “next generation” applications of wearable technology, but these face certain technical hurdles. Two main obstacles are Internet of Things (IoT) aggregation and augmented reality tools. IoT packet aggregation requires high bandwidth to support throughput of all the sensors and devices connected within the network. Augmented reality, such as that used by remote collaboration headsets and digital eyewear, has strict latency requirements - in the 20 to 100 milliseconds (ms) range - to keep the projected image locked into the correct place and avoid causing nausea and dizziness to the user.

The need for high performance

The challenge of achieving deterministic high bandwidth and low latency to support wearable technology is not trivial. Since wearables are essentially endpoints in the network, they reside at the far reaches of the network edge, where bandwidth and latency prove most demanding. The issues implicit in delivering high throughput to wearables while achieving ultra-low latency are similar to the challenges faced by telecom operators who are working to deploy 5G networks.

The easiest way to achieve such high performance at the network edge is to move the data processing and forwarding closer to the end users. This poses its own challenges, though, as there is limited space and power at the edge. There is no room for monolithic, single-function application-specific integrated circuit (ASIC)-based appliances to provide the necessary performance, so a solution is needed that can take advantage of existing networking equipment while accelerating the data path.

Network Function Virtualization (NFV) has proven to be a breakthrough; by performing necessary networking and security functions in software installed on standard x86 servers in small edge locations, it is possible to gain necessary flexibility and agility at the edge. However, there is a limit to the performance attainable when standard CPUs are running networking software, and it often requires even more space because the functions are so CPU-intensive that too many cores are required for the process, necessitating multiple expensive servers to handle the job. When it comes to very high bandwidth and low latency, CPU-based software networking alone is simply not sufficient.

The solution must provide the performance of an ASIC with the agility of software. The answer is to offload the virtual functions to hardware, providing the necessary acceleration while maintaining flexibility.

Specific wearables use cases

The Internet of Things (IoT) is on the cusp of a major adoption into all aspects of our lives. In many ways, it is already being used extensively in various applications. Although IoT itself is not generally challenged by bandwidth or latency issues, when it comes to the networking components that aggregate IoT packets, the required bandwidth spikes dramatically. Similarly, IoT has technical requirements such as time-sensitive switching, header compression, data load balancing, hierarchical quality of service, and encryption/decryption at wirespeed, all of which are extremely CPU-intensive operations. Without hardware-based data path offload, IoT will struggle to achieve the necessary performance.

Augmented reality (AR) is a use case that is highly latency-sensitive. Although Google Glass seems to have come and gone, we are now seeing a movement by Google and others to market AR solutions to technicians and health operators to make their tasks easier, more efficient, and safer. Consider, for example, a technician who needs to fix some part of a system. Imagine that he needs to alternate his attention between looking up technical documentation on his phone and the actual workpiece. The potential for costly or harmful mistakes is very high.

Now consider this operation with AR, integrating artificial intelligence that anticipates the technician’s needs. The augmented reality device can either be used to overlay technical schematics onto the physical workpiece or simply as another “screen” (where reality provides the first screen). In the very simplest implementation, this means hands-free assistance. With sophisticated AI, it can make the task far easier, clearer, and faster.

A similar example of this use of augmented reality is “smart measuring tape” which can lock onto whatever the technician is viewing. This can overlay the workpiece with all kinds of relevant measurement information, making the worker’s task far easier and more hands free, further increasing safety.

In any use of AR, latency is key. As soon as visual latency exceeds 20-100ms, headaches, dizziness, and nausea set in, negating all the benefits of ease-of-use and clarity intended by the AR solution in the first place.

Another concern when it comes to integrating wearables into our lives is security and privacy. All users want their personal information to remain secure, but nowhere more so than in healthcare, with wearables such as biosensors and pacemakers. Not only do these wearables contain vast amounts of sensitive personal information about the user’s health, they also control and monitor critical health functions that must run at all times and be highly secure.

In order to enable the IoT infrastructure, low-latency augmented reality, and the highly secure data path that is the foundation of wearable technology, we need hardware-based acceleration at the network edge. There are various hardware technologies capable of offloading certain network functions, but none accomplish full offload of the data plane as well as field-programmable gate arrays (FPGAs).

FPGA as a platform to accelerate wearables

FPGAs are programmable hardware and offer the performance of an ASIC with the flexibility of software. Because of their parallel processing capabilities and highly pipelined architecture, FPGAs are optimized to handle CPU-intensive networking and security functions efficiently. This enables very high bandwidth and better ability to scale for high throughput applications. That’s why FPGA SmartNICs are indispensable in next-generation networks.

FPGA SmartNICs are also very effective in reducing latency and jitter. By using an FPGA to handle data processing, it is feasible to achieve a latency around or below one millisecond, because the data path avoids the CPU entirely. Instead, the data is entirely offloaded from the CPU to the FPGA on the network interface card. By comparison, when software on a CPU is used for networking, latency lower than 50-100ms is considered very good.

The upper image shows a standard network interface card on an x86 server, whereby several CPU cores are used to process data. In the lower image, an FPGA-based SmartNIC enables full offload of the data plane from the CPUs to the FPGA, improving performance and freeing many more CPU cores for user applications.

Another important advantage of offloading the data path from CPUs is in the area of cybersecurity. If the data never needs to reach the CPU, the networking is entirely separated from the compute function. Should the CPU - which is much more vulnerable to breaches than an FPGA - be hacked, the data path (handled by the FPGA) is still protected. The FPGA also can efficiently handle security functions such as encryption and decryption, access control list, and firewall, thereby reducing the load on the CPU.

Beyond meeting the bandwidth, latency, and security requirements of wearable implementations, FPGAs also have the benefit of being open, programmable and configurable hardware and a perfect complement to commercial off-the-shelf servers since they are general purpose and agile. Their full reprogrammability means that they are futureproof, as hardware does not need to be replaced or upgraded when new functionalities and features emerge. The FPGA SmartNIC can be reprogrammed as needed instead of replacing the whole card if the application or use case changes.

FPGA-based SmartNICs provide unmatched scalability to enable communication service providers to easily handle large numbers of subscribers and devices at cost without significantly adding latency and power. This is crucial for wearable technology, which will expand to ever-more network endpoints as the technology evolves and use cases become more prominent.

Wearable technology is poised to dramatically improve the day-to-day tasks of many technical workers in industrial and healthcare settings, while simultaneously improving efficiencies and bottom lines. In order to make this vision a reality, though, certain key parts of the IoT and wearable system require FPGA SmartNIC acceleration to meet their challenging requirements.

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Author

David Levi is CEO of Ethernity Networks. He has spent more than 25 years in the telecommunications industry, including founding a semiconductor company that was later acquired by a major telecoms vendor. He holds two U.S. patents.

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